This invention generally relates to semiconductor memory devices and more specifically to static random access memory systems having both volatile and non-volative binary data storage capability. Semiconductor memories generally fall into three categories: read only memory (ROM), random access memory (RAM), and serial access memory (SAM).
A ROM is typically employed where a fixed bit pattern is required, such as for a firmware or microcode program in a computer system. However, within the general category of ROMs there are programmable read only memories (PROMs), erasable PROMs (EPROMs) and electrically-alterable read only memories (EAROMs) which are sometimes designated electrically erasable PROMs (EEPROMs). PROMs have the characteristic that they can be written one time only to a selected bit pattern which thereafter becomes fixed. EPROMs can be electrically programmed to a preselected bit pattern, but they typically require ultraviolet light shined on the device to erase the stored bit pattern. This usually requires the EPROM device to be removed from the circuit in which it is used. EEPROMs can be electrically erased and reprogrammed in the circuit environment in which they are being used. While both EPROMs EEPROMs have the capability of altering the bit pattern stored therein, the substantial time required for erasing and re-programming precludes their use as random access memory devices in memory systems which require very rapid changing of some or all of the stored bit pattern.
Semiconductor SAM devices generally fall into the charge-coupled device memory (CCDM) or bubble domain memory (BDM) categories. CCDM and BDM systems typically involve single or multiple serial data loops with access to data stored at any particular location typically requiring serial shifting of each bit of data to a location where it can be accessed for reading or writing. Semiconductor SAM systems are thus typically employed where large amounts of data need to be stored but very rapid access to any particular data bit is not required.
Semiconductor RAMs generally fall into two categories: static RAMs and dynamic RAMs. Static RAMs typically employ cells comprising bistable multivibrator or flip-flop circuits with the stored bit value determined by which of its two bistable states the circuit is in. Dynamic RAMs typically employ a cell arrangement in which the stored bit value is determined by the presence or absence of a voltage stored on a semiconductor capacitor structure. Since static RAMs employ bistable devices, the bit content of each cell is retained without refreshing and the readout of the bit content is non-destructive. Dynamic RAMs on the other hand typically require periodic refreshing of the information stored on the capacitor although the readout may be either destructive or non-destructive depending on the cell design.
All versions of ROMs are inherently non-volatile, including EPROMs and EEPROMs, due either to the ROM cell design or to the electrical characteristics of the devices employed in each ROM cell. RAMs, on the other hand, are generally volatile devices, i.e., the bit content of the memory is typically lost if electric power to the RAM is removed or lost. However, over the past decade or so, various approaches have been taken to adding backup non-volatile storage capability to RAMs. The invention set forth herein falls generally into the field of RAMs in which non-volatile semiconductor memory devices are employed in each RAM cell to provide backup non-volatile data storage capability. In general, static RAM cells can be provided with non-volatile backup data storage capability by adding non-volatile, threshold-alterable devices of the transistor or capacitor variety to the RAM cell. These cells will be referred to as volatile/non-volatile RAM cells or simply V/NV RAM cells.
V/NV RAM cells incorporating non-volatile transistors are disclosed in the following exemplary references: Mark et al. U.S. Pat. No. 3,636,530; Lockwood U.S. Pat. No. 3,676,717; an article by Frohman-Bentchkowsky, entitled "The Metal-Nitride-Oxide-Silicon (MNOS) Transistor--Characteristics and Applications", "Proceedings of the IEEE", Vol. 58, No. 8, August 1970 (Page 1218); Uchida et al. U.S. Pat. No. 3,950,737; and Uchida U.S. Pat. No. 4,044,343. V/NV RAM cells employing non-volatile transistor backup devices have been employed in non-volatile counter circuits manufactured by various companies for electronic artillery fuse applications and for other general purpose uses. They are also employed in several V/NV RAM integrated circuits (ICs) commercially available from several companies.
V/NV RAM cells using non-volatile capacitor elements are disclosed in the following exemplary prior art references: Ho et al. U.S. Pat. No. 3,662,351; copending Aneshansley U.S. application Ser. No. 947,927, filed Oct. 2, 1978, (having an effective filing date of Sept. 5, 1975, for parent application Ser. No. 610,813); Schuermeyer et al. U.S. Pat. No. 4,091,460; copending Lockwood U.S. application Ser. No. 020,124, filed Mar. 13, 1979; and Uchida et al. Japanese Disclosure No. 53-72429, published June 27, 1978.
In general, V/NV RAM cells employing non-volatile capacitors require fewer active semiconductor devices than do V/NV RAM cells employing non-volatile transistors. Since the general trend of the semiconductor industry is toward producing ICs with higher bit storage densities and since V/NV RAM cells having fewer active devices per cell occupy less "real estate" on an IC chip, it is anticipated that the trend will be toward usage of V/NV RAM cells with non-volatile capacitor devices. Another advantage of such cells is that one fewer control signal lines are required to be routed to each cell, and thus one less control signal need be provided to the IC chip. This further reduces chip real estate and eliminates one pin-out on the IC chip.
The present commercial versions of V/NV RAM ICs generally employ the RAM cell structure shown in FIG. 1 of the Uchida '343 patent (a virtually identical cell structure also being shown in FIG. 10 of the Mark et al. '530 patent). These V/NV RAM cells employ bypass transistors in parallel with the non-volatile memory transistors in the load circuits of the cell with a separate control line provided to these bypass transistors to turn them off when information is being read out of the non-volatile memory transistors and to turn them on when the cell is operating in the normal volatile mode. The bypass transistors and the control lines thereto add substantially to the "real estate" consumed by each V/NV RAM cell, and the control line further requires a separate pin-out on the IC chip.
The V/NV RAM cell disclosed in the Schuermeyer et al. '460 patent involves the smallest number of active devices of any of the prior art non-volatile RAM cells known to me. This results from using only a single pair of split-gate, non-volatile, threshold-alterable capacitors in each cell as both charge pump, low current load impedances and backup non-volatile memory devices. However, while the Schuermeyer et al. V/NV RAM cell could be manufactured with the highest number of cells per unit area of an IC chip, it requires that the charge pump line be provided with a relatively high frequency charge pump signal during normal volatile operation of the V/NV RAM Cell. Typically, V/NV RAM ICs are used in systems which employ a substantial number of such ICs to provide the total memory bit capacity required. Present n-channel SIS device technology could provide IC chips using the Schuermeyer et al. V/NV RAM cell having a total of 4,096 memory cells on each chip. Driving each chip would require a substantial AC current supply due to the relatively large total capacitance of the 8,192 alterable capacitors being driven in parallel by the high frequency charge pump signal. When multiples of such chips are employed, the total demand for AC charge pump current is multiplied by the number of chips. The Schuermeyer et al. V/NV RAM cell thus has the disadvantage of requiring that the system designer provide an AC charge pump signal of high current capacity. This special AC signal would generally not be useful in any other portion of a data processing system environment in which these types of memory chips are typically used.
FIG. 1A of the drawings herein shows a prior art V/NV RAM cell employing non-volatile capacitor structures instead of non-volatile transistor structures. It should be apparent that fewer active devices are used in this type of cell and thus the chip real estate consumed by such memory cell is substantially less. FIG. 1A is structurally equivalent to the V/NV RAM cell disclosed in FIG. 4 of the above-referenced Aneshansley application. The only difference is that a preferred split-gate, non-volatile capacitor structure is schematically depicted in FIG. 1A, whereas the more general non-volatile capacitor symbol is used in FIG. 4 of the Aneshansley application. This split gate non-volatile capacitor structure is disclosed in Chang et al. U.S. Pat. No. 3,911,464 (e.g. FIGS. 9 and 10), the disclosure of which is specifically incorporated herein by reference. The structure and operation of the V/NV RAM cell disclosed in the Aneshansley application results in inversion of the data during a power-up, non-volatile/volatile restore operation (hereinafter simply called a "NV/V restore operation"). Those skilled in the semiconductor art will appreciate that, if the prior art N/NV RAM cell shown in FIG. 1A were implemented in a straightforward manner in a five volt, n-channel, semiconductor-insulator-semiconductor (SIS) device technology, the enhancement load transistors would be changed to high semiconductor resistors or high impedance depletion mode devices to reduce the power consumption of the cell. However, this straightforward adaptation to this currently highest state of the art technology would result in a marginal differential voltage threshold window between the two non-volatile capacitors after a power-down, volatile/non-volatile write operation (hereinafter simply called a "V/NV write operation"). This results because the five volt signal on one of output nodes does not provide effective channel shielding in one of the non-volatile capacitors during the V/NV write operation. This is explained in more detail below.
FIG. 1B of the drawings herein shows a prior art V/NV RAM cell which employs non-volatile capacitor structures and utilizes both a semiconductor resistance element and a field effect transistor of the enhancement type in the load circuit of the multivibrator. FIG. 1B is disclosed in the above-referenced Lockwood application and constitutes an improvement over the cell disclosed in the above-referenced Aneshansley application in that the utilization of the enhancement type field effect transistor in the load circuits of the multivibrator provides a bootstrapped voltage on one of the output nodes during a V/NV write operation to provide a more effective channel shielding voltage to one of the non-volatile capacitors. However, the presence of the bootstrapped voltage on one of the output nodes of the multivibrator circuit requires that the switching transistors in the multivibrator be constructed with relatively long channel lengths to handle the bootstrapped voltage magnitude. Accordingly, these switching transistors occupy a substantial amount of chip real estate.
The V/NV RAM cell disclosed in the above-referenced Uchida et al. Japanese Disclosure also involves the production of a bootstrap voltage on the output nodes of the multivibrator. Consequently, that cell has the same inherent disadvantage of requiring large switching transistors to withstand the bootstrapped voltage.